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NXP Semiconductors /LPC11E6x /DMA /ENABLECLR0

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Interpret as ENABLECLR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLR

Description

Channel Enable Clear for all DMA channels.

Fields

CLR

Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears the channel enable bit n.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data